SN74ACT3641
1024 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS338B - JANUARY 1994 - REVISED SEPTEMBER 1995

features

• Free-Running CLKA and CLKB Can Be Asynchronous or Coincident
• Clocked FIFO Buffering Data From Port A to Port B
• Memory Size: 1024 × 36
• Synchronous Read-Retransmit Capability
• Mailbox Register in Each Direction
• Programmable Almost-Full and Almost-Empty Flags
• Microprocessor Interface Control Logic
• Input-Ready (IR) and Almost-Full () Flags Synchronized by CLKA
• Output-Ready (OR) and Almost-Empty () Flags Synchronized by CLKB
• Low-Power 0.8-Micron Advanced CMOS Technology
• Supports Clock Frequencies up to 67 MHz
• Fast Access Times of 11 ns
• Pin-to-Pin Compatible With the SN74ACT3631 and SN74ACT3651
• Available in Space-Saving 120-Pin Thin Quad Flat (PCB) and 132-Pin Plastic Quad Flat (PQ) Packages

description

The SN74ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 12 ns. The 1024 × 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths. Expansion is also possible in word depth.

The SN74ACT3641 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control.

The input-ready (IR) flag and almost-full () flag of the FIFO are two-stage synchronized to CLKA. The output-ready (OR) flag and almost-empty () flag of the FIFO are two-stage synchronized to CLKB. Offset values for the almost-full and almost-empty flags of the FIFO can be programmed from port A or through a serial input.

The SN74ACT3641 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the application reports FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering and FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control in the 1996 High-Performance FIFO Memories Designer's Handbook, literature number SCAA012A.