SCAS340C - MARCH 1994 - REVISED JANUARY 1997
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This 3-line to 8-line decoder/demultiplexer with latches on three address inputs is designed for 2.7-V to 3.6-V VCC operation.
The SN74LVC137A is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
When the latch-enable (G\2A) input is low, the SN74LVC137A acts as a decoder/demultiplexer. When G\2A transitions from low to high, the address present at the inputs (A, B, and C) is stored in the latches. Further address changes are ignored, provided G\2A remains high. The output-enable (G1 and G\2B) inputs control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G\2B is high.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
The SN74LVC137A is characterized for operation from -40°C to 85°C.