SN74LVC139A
DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER

SCAS341C - MARCH 1994 - REVISED JANUARY 1997

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features

• EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
• Inputs Accept Voltages to 5.5 V
• Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages

  EPIC is a trademark of Texas Instruments Incorporated.

   

description

This dual 2-line to 4-line decoder/demultiplexer is designed for 2.7-V to 3.6-V V_CC operation.

The SN74LVC139A is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The device comprises two individual 2-line to 4-line decoders in a single package. The active-low output-enable () input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

The SN74LVC139A is characterized for operation from -40°C to 85°C.