SN74LVC243
QUADRUPLE BUS TRANSCEIVER
WITH 3-STATE OUTPUTS

SCAS344 - MARCH 1994

features

• EPIC ^TM (Enhanced-Performance Implanted CMOS) Submicron Process
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
• Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages

  EPIC is a trademark of Texas Instruments Incorporated.

description

This quadruple bus transceiver is designed for 2.7-V to 3.6-V V_CC operation.

The SN74LVC243 is designed for asynchronous communications between data buses. The control-function implementation allows for maximum flexibility in timing. The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the output-enable (OEBA and ) inputs. The output-enable inputs can be used to disable the device so that the buses are effectively isolated.

The dual-enable configuration gives the quadruple bus transceivers the capability to store data by simultaneous enabling of OEBA and . Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (eight in all) remain at their states. The 4-bit codes appearing on the two sets of buses will be identical for the SN74LVC243.

The SN74LVC243 is characterized for operation from -40°C to 85°C.