SN74LVC544A
OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS

SCAS346C - MARCH 1994 - REVISED JANUARY 1997

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features

• EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
• Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V V_CC)
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages

EPIC is a trademark of Texas Instruments Incorporated.

description

This octal registered transceiver is designed for 2.7-V to 3.6-V V_CC operation.

The SN74LVC544A contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable ( or ) and output-enable ( or ) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable () input must be low to enter data from A or to output data from B. If is low and is low, the A-to-B latches are transparent; a subsequent low-to-high transition of places the A latches in the storage mode. With and both low, the 3-state B outputs are active and reflect the inverted data present at the output of the A latches. Data flow from B to A is similar to A to B, but requires using the , , and .

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

The SN74LVC544A is characterized for operation from -40°C to 85°C.

A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA\, LEBA\, and OEBA\.

Output level before the indicated steady-state input conditions were established