CDC2536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS

SCAS377B - APRIL 1994 - REVISED NOVEMBER 1995

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

Low Output Skew for Clock-Distribution and Clock-Generation Applications
Operates at 3.3-V V_CC
Distributes One Clock Input to Six Outputs
One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency
No External RC Network Required
On-Chip Series Damping Resistors
External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
Application for Synchronous DRAM, High-Speed Microprocessor
TTL-Compatible Inputs and Outputs
Outputs Drive 50- Parallel-Terminated Transmission Lines
State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
Distributed V_CC and Ground Pins Reduce Switching Noise
Packaged in Plastic 28-Pin Shrink Small-Outline Package
EPIC-IIB is a trademark of Texas Instruments Incorporated.

description

The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with syncronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC2536 operates at 3.3-V V_CC and is designed to drive a properly terminated 50- transmission line. The CDC2536 also provides on-chip series-damping resistors, eliminating the need for external termination components.

The feedback (FBIN) input is used to synchronize the output clocks in frequency and phase to the input clock (CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clock.

Output-enable () is provided for output control. When is high, the outputs are in the high-impedance state. When is low, the outputs are active. is negative-edge triggered and can be used to reset the outputs operating at half frequency. TEST is used for factory testing of the device and can be use to bypass the PLL. TEST should be strapped to GND for normal operation.

Unlike many products containing PLLs, the CDC2536 does not require external RC networks. The loop filter for the PLL is included on chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2536 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of SEL, enabling the PLL via TEST, and upon enable of all outputs via .

The CDC2536 is characterized for operation from 0°C to 70°C.

detailed description of output configurations

The voltage-controlled oscillator (VCO) used in the CDC2536 has a frequency range of 100 MHz to 200 MHz, twice the operating frequency of the CDC2536 outputs. The output of the VCO is divided by two and by four to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. SEL determines which of the two signals are buffered to each bank of device outputs.

One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the frequency of the output matches that of CLKIN. In the case that a VCO/2 output is wired to FBIN, the VCO must operate at twice the CLKIN frequency resulting in device outputs that operate at either the same or one-half the CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at the same or twice the CLKIN frequency.

output configuration A

Output configuration A is valid when any output configured as a 1x frequency output in Table 1 is fed back to FBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputs configured as 1/2x outputs operate at half the CLKIN frequency, while outputs configured as 1x outputs operate at the same frequency as CLKIN.

NOTE: n = 1, 2, 3

output configuration B

Output configuration B is valid when any output configured as a 1x frequency output in Table 2 is fed back to FBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputs configured as 1x outputs operate at the CLKIN frequency, while outputs configured as 2x outputs operate at double the frequency of CLKIN.