74AC11162SYNCHRONOUS 4-BIT DECADE COUNTER

SCAS381 - D3199, AUGUST 1988 - REVISED APRIL 1993

features

• Internal Look-Ahead Circuitry for Fast Counting
• Carry Output for N-Bit Cascading
• Fully Synchronous Operation for Counting
• Synchronously Programmable
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
• EPIC ^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

  EPIC is a trademark of Texas Instruments Incorporated.

description

This synchronous, presettable 4-bit decade counter features an internal carry look-ahead circuitry for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple-clock) counters; however, counting spikes may occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock-input waveform.

These counters are fully programmable in that they may be preset to any number between 0 and 9. As presetting is synchronous, setting up a low level at the load () input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs.

If one of these decade counters is preset to a number between 10 and 15 or assumes such an invalid state when power is applied, it progresses to the normal sequence within two counts as shown in the state diagram.

The clear function for the 74AC11162 is synchronous, and a low level at the clear () input drives all four of the flip-flop outputs low after the next low-to-high transition of the clock regardless of the levels on the count-enable (ENP and ENT) inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to the clear input to synchronously clear the counter to 0000 (LLLL on the Q outputs).

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable (ENP and ENT) inputs and a ripple-carry (RCO) output. Both ENP and ENT must be high to count, and ENT is fed foward to enable RCO. RCO thus enabled produces a high-level pulse while the count is 9 (HLLH). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at the ENP or ENT inputs are allowed regardless of the level of the clock input.

These counters feature fully independent clock circuits. Changes at control inputs (ENP, ENT, or ) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold times.

The 74AC11162 is characterized for operation from -40°C to 85°C.