54ACT11833, 74ACT118338-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

features

• Inputs are TTL-Voltage Compatible
• High-Speed Bus Transceivers with Parity Generator/Checker
• Parity-Error Flag Open-Drain Output
• Register for Storage of the Parity-Error Flag
• Flow-Through Architecture to Optimize PCB Layout
• Center-Pin V_CC and GND Configurations to Minimize High-Speed Switching Noise
• EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

description

The 'ACT11833 is an 8-bit to 9-bit parity transceiver designed for two-way communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the output will indicate whether or not an error in the B data has occurred. The output enable inputs and can be used to disable the device so that the buses are effectively isolated.

A 9-bit parity generator/checker generates a parity-odd output (PARITY) and monitors the parity of the I/O ports with an open-drain parity error flag (). is clocked into the register on the rising edge of the CLK input. The error flag register is cleared with a low pulse on the input. When both and are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability.

The 54ACT11833 is characterized for operation over the full military temperature range of - 55°C to 125°C. The 74ACT11833 is characterized for operation from - 40°C to 85°C.