m Process
54AC11881, 74AC11881
ARITHMETIC LOGIC/FUNCTION GENERATORS
m Process
[dagger] This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for DW, JT, and NT packages.
In both Figures 1 and 2, the polarity indicators
( ) indicate that the associated input or output is active-low with respect to the function shown inside the symbol and the symbols are the same in both figures. The signal designations in Figure 1 agree with the indicated internal functions based on active-low data and are for use with the logic functions and arithmetic operations shown in Table 1. The signal designations have been changed in Figure 2 to accommodate the logic functions and arithmetic operations for the active-high data given in Table 2.
Pin numbers shown are for DW, JT, and NT packages.
The ´AC11881 arithmetic logic units (ALU)/function generators have a complexity of 77 equivalent gates on a monolithic chip. These circuits perform 16 binary arithmetic operations on two 4-bit words as shown in Tables 1 and 2. These operations are selected by the four function-select lines (S0, S1, S2, S3) and include addition, subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal carries must be enabled by applying a low-level voltage to the mode control input (M). A full carry look-ahead scheme is made available in these devices for fast, simultaneous carry generation by means of two cascade-outputs, G\ and P\, for the four bits in the package. When used in conjunction with the 54AC11882 or 74AC11882 full carry look-ahead circuits, high-speed arithmetic operations can be performed. The typical addition times shown previously illustrate the little additional time required for addition of longer words when full carry look-ahead is employed. The method of cascading ´AC11882 circuits with these ALUs to provide multilevel full carry look-ahead is illustrated under signal designations.
If high speed is not of importance, a ripple-carry input (Cn) and a ripple-carry output (Cn+4) are available. However, the ripple-carry delay has also been minimized so that arithmetic manipulations for small word lengths can be performed without enternal circuitry.
The 'AC11881 will accommodate active-high or active-low data if the pin designations are interpreted as follows:
Subtraction is accomplished by 1's complement addition, where the 1's complement of the subtrahend is generated internally. The resultant output is A-B-1, which requires an end-around or forced carry to provide A-B.
The ´AC11881 can also be utilized as a comparator. The A=B output is internally decoded from the function outputs (F0, F1, F2,F3) so that when two words of equal magnitude are applied at the A and B inputs, it will assume a high level to indicate equality (A=B). The ALU must be in the subtract mode with Cn=H when performing this comparison. The A=B output is open-collector so that it can be wire-AND connected to give a comparison for more than four bits. The carry output (Cn+4) can also be used to supply relative magnitude information. Again, the ALU must be placed in the subtract mode by placing the function select input S3, S2, S1, S0 at L, H, H, L, respectively.
These circuits have been designed to not only incorporate all of the designer's requirements for arithmetic operations, but also to provide 16 possible functions of two Boolean variables without the use of external circuitry. These logic functions are selected by use of the four function-select inputs (S0, S1, S2, S3) with the mode-control input (M) at a high level to disable the internal carry. The 16 logic functions are detailed in Tables 1 and 2 and include exclusive-OR, NAND, AND, NOR, and OR functions.
The ´AC11881 has the same pinout and same functionality as
the ´AC11181 except for the P\, G\, and
Cn + 4 outputs when the device is in the logic mode (M =
H).
In the logic mode, the ´ACT11881 provides the user with a status check on the input words A and B and the output word F. While in the logic mode, the P\, G\, and Cn + 4 outputs supply status information based upon the following logical combinations:
P\ = F0 + F1 + F2 + F3
G\ = H
Cn + 4 = PCn.
The combination of signals on the S3 through S0 control lines determine the operation performed on the data words to generate the output bits F\i. By monitoring the P\ and Cn + 4 outputs, the user can determine if all pairs of input bits are equal (see table above) or if any pair of inputs are both high (see table above). The ´ACT11881 has the unique feature of providing an A = B status while the exclusive-OR ( no map ) function is being utilized. When the control inputs (S3, S2, S1, S0) equal H, L, L, H; a status check is generated to determine whether all pairs (A\i, B\i) are equal in the following manner: P\ = (A0 no map B0) + (A1 no map B1) + (A2 no map B2) + (A3 no map B3). This unique bit-by-bit comparison of the data words, which is available on the totem-pole P\ output, is particularly useful when cascading ´ACT11881s. As the A = B condition is sensed in the first stage, the signal is propagated through the same ports used for carry generation in the arithmetic mode (P\ and G\). Thus, the A = B status is transmitted to the second stage more quickly without the need for external multiplexing logic. The A = B open-drain output allows the user to check the validity of the bit-by-bit result by comparing the two signals for parity.
If the user wishes to check for any pair of data inputs (A\i, B\i) being high, it is necessary to set the control lines (S3, S2, S1, S0) to L, H, L, L. The data pairs will then be ANDed together and the results ORed in the following manner: P\ = A\0B\0 +A\1B\1 + A\2B\2 +A\3B\3.
[dagger] Each bit is shifted to the next more significant position.