m Process
m Process
In both Figures 1 and 2, the polarity indicators (
) indicate that the associated
input or output is active-low with respect to the function shown
inside the symbol, and the symbols are the same in both figures. The
signal designations in Figure 1 agree with the indicated internal
functions based on active-low data, and are for use with the logic
functions and arithmetic operations shown in Table 1. The signal
designations have been changed in Figures 2 to accommodate the logic
functions and arithmetic operations for the active-high data given in
Table 2.
The 'ACT11881 arithmetic logic unit (ALU)/function generators have a complexity of 77 equivalent gates on a monolithic chip. These circuits perform 16 binary arithmetic operations on two 4-bit words as shown in Tables 1 and 2. These operations are selected by the four function-select lines (S0, S1, S2, S3) and include addition, subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal carries must be enabled by applying a low-level voltage to the mode control input (M). A full carry look-ahead scheme is made available in these devices for fast, simultaneous carry generation by means of two cascade-outputs, G\ and P\, for the four bits in the package. When used in conjunction with the 54ACT11882 or 74ACT11882 full carry look-ahead circuits, high-speed arithmetic operations can be performed. The typical addition times shown previously illustrate the little additional time required for addition of longer words when full carry look-ahead is employed. The method of cascading 'ACT11882 circuits with these ALUs to provide multilevel full carry look-ahead is illustrated under signal designations.
If high speed is not of importance, a ripple-carry input (Cn) and a ripple-carry output (Cn + 4) are available. However, the ripple-carry delay has also been minimized so that arithmetic manipulations for small word lengths can be performed without external circuitry.
The 'ACT11881 will accommodate active-high or active-low data if the pin designations are interpreted as follows:
Subtraction is accomplished by 1's complement addition, where the 1's complement of the subtrahend is generated internally. The resultant output is A-B-1, which requires an end-around or forced carry to provide A-B.
The 'ACT11881 can also be used as a comparator. The A=B output is internally decoded from the function outputs (F0, F1, F2, F3) so that when two words of equal magnitude are applied at the A and B inputs, it will assume a high level to indicate equality (A=B). The ALU must be in the subtract mode with Cn=H when performing this comparison. The A=B output is open-collector so that it can be wired-AND connected to give a comparison for more than four bits. The carry output (Cn + 4) can also be used to supply relative magnitude information. Again, the ALU must be placed in the subtract mode by placing the function select input S3, S2, S1, S0 at L, H, H, L, respectively.
These circuits have been designed to not only incorporate all of the designer's requirements for arithmetic operations, but also to provide 16 possible functions of two Boolean variables without the use of external circuitry. These logic functions are selected by use of the four function-select inputs (S0, S1, S2, S3) with the mode-control input (M) at a high level to disable the internal carry. The 16 logic functions are detailed in Tables 1 and 2 and include exclusive-OR, NAND, AND, NOR, and OR functions.
The 'ACT11881 has the same pinout and same functionality as the 'ACT11181 except for the P\, G\, and Cn + 4 outputs when the device is in the logic mode (M = H).