54AC16471,54ACT16471
74AC16471,74ACT16471
16-BIT REGISTERD BUS TRANCEIVERS WITH 3-STATE OUTPUTS
SCAS396 - JUNE 1990

features

• Members of Texas Instruments Widebus^TM Family
• Packaged in Shrink Small-Outline 300-mil Packages (SSOP) and 380-mil Fine-Pitch Ceramic Flat Packages Using 25-mil Center-to-Center Pin Spacings
• Inputs are TTL- or CMOS-Voltage Compatible
• 3-State Outputs Drive Bus Lines Directly
• Flow-Through Architecture Optimizes PCB Layout
• Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
• EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C

description

The 'AC16471 and 'ACT16471 are inverting 16-bit registered bus transceivers composed of two 8-bit sections with separate control signals. For either 8-bit transceiver section, data flow in the A-to-B mode is controlled by output-enable (1 or 2), direction-enable (1 or 2), and clock (1CLKAB or 2CLKAB) inputs.

When 1(or 2) is high, storage of the current A-bus data is inhibited and the corresponding B outputs are in the high-impedance state.When 1 (or 2) is low, the register contents and the output buffers are controlled by 1CLKAB (or 2CLKAB) and 1 (or 2). A low level on 1CLKAB (or 2 CLKAB) inhibits loading of the registers with the current A-bus data; a low-to-high transition on 1CLKAB (or 2CLKAB) causes the corresponding registers to be loaded with the current A-bus data. If 1 (or 2) is low, the corresponding B outputs reflect the inverse of the register contents. A high level on 1 (or 2) causes the B outputs to be in the high-impedance state.