54AC16473, 54ACT16473
74AC16473, 74ACT16473
18-BIT LATCHED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SCAS398 - JUNE 1990

features

• Members of Texas Instruments Widebus^TM Family
• Packaged in Shrink Small-Outline 300-mil Packages (SSOP) and 380-mil Fine-Pitch Ceramic Flat Packages Using 25-mil Center-to-Center Pin Spacings
• Inputs are TTL- or CMOS-Voltage Compatible
• 3-State Outputs Drive Bus Lines Directly
• Flow-Through Architecture Optimizes PCB Layout
• Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
• EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C

description

The 'AC16473 and 'ACT16473 are inverting 18-bit latched bus transceivers composed of two 9-bit sections with separate control signals. For either 9-bit transceiver section, data flow in the A-to-B mode is controlled by output enable (1 or 2) and latch enable (1 or 2) inputs. When 1 (or 2) is low, the corresponding B outputs are active (high or low logic levels). When 1 (or 2) is high, the corresponding B outputs are in the high-impedance state. The latches retain their prior states when 1 (or 2) is high and reflect the states of the corresponding A inputs when 1 (or 2) is low.

function table, each section^[dagger]