54AC16843, 54ACT16843
74AC16843, 74ACT16843
18-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCAS407 - JUNE 1990

features

• Members of Texas Instruments Widebus^TM Family
• Packaged in Shrink Small-Outline 300-mil Packages (SSOP) and 380-mil Fine-Pitch Ceramic Flat Packages Using 25-mil Center-to-Center Pin Spacings
• Inputs are TTL- or CMOS-Voltage Compatible
• 3-State Outputs Drive Bus Lines Directly
• Flow-Through Architecture Optimizes PCB Layout
• Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
• EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C

description

The 'AC16843 and 'ACT16843 are noninverting 18-bit D-type latches composed of two 9-bit sections with separate control signals. For each 9-bit section, when the enable input 1C (or 2C) is low, the latches are in the storage mode. In contrast, when 1C (or 2C) is high, the latches are transparent. In this mode, data present at the 1D (or 2D) inputs is transmitted to the 1Q (or 2Q) outputs if 1 (or 2) is low. If 1 (or 2) is high, the corresponding outputs are in the high-impedance state.

Preset (1PRE\ and 2PRE\) and clear (1 and 2) inputs are provided to set the corresponding Q outputs asynchronously to a high or low logic level. Taking 1PRE\ (or 2PRE\) low sets the corresponding outputs high. If 1PRE\ (or 2PRE\) is high, taking 1 (or 2) low sets the corresponding outputs low.

The 74AC16843 and 74ACT16843 are packaged in TI's shrink small-outline package (SSOP) with 25-mil center-to-center pin spacings. This package provides twice the I/O pin count and functionality of a standard small-outline package in the same printed-circuit-board area.

The 'AC16843 has CMOS-compatible input thresholds. The 'ACT16843 has TTL-compatible input thresholds.

The 54AC16843 and 54ACT16843 are characterized over the full military temperature range of -55°C to 125°C. The 74AC16843 and 74ACT16843 are characterized for operation from -40°C to 85°C.