CDC338
PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS

MAY 1992 - REVISED FEBRUARY 1993

features

• Replaces SN74ABT338
• Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
• State-of-the-Art EPIC-IIB ^TM BiCMOS Design Significantly Reduces Power Dissipation
• TTL-Compatible Inputs and TTL Outputs
• Distributes One Clock Input to Six Outputs
  • Four Same-Frequency Outputs
  • One Half-Frequency Outputs
  • One Double-Frequency Output
• Output Duty Cycle Correction to 50%
• No External RC Network Required
• Edge-Triggered Clear for Half-Frequency Output
• Distributed V_CC and Ground Pins Reduce Switching Noise
• High-Drive Outputs (-48-mA I_OH,48-mA I_OL)
• Packaged in Plastic Small-Outline Package

EPIC-IIB is a trademark of Texas Instruments Incorporated.

description

The CDC338 is a high-performance, low-skew, low-jitter clock driver. It uses phase-lock loops (PLLs) to precisely align, in both frequency and phase, the clock output signals to the clock (CLKIN) input signal. It is specifically designed for use with popular microprocessors operating at speeds from 15 MHz to 35 MHz or up to 70 MHz using the double-frequency (DF) output.

The four Y outputs switch in phase and at the same frequency as CLKIN. The half-frequency (HF) output operates at one-half the CLKIN frequency, and DF operates at twice the CLKIN frequency. All output signal duty cycles are adjusted to 50% independent of the duty cycle at CLKIN.

Output-enable () and clear () inputs are also provided for output control and synchronization. When is high, the outputs are in the high-impedance state. When is low, the outputs are active. The input is negative-edge-triggered and is provided to allow phase synchronization of the HF outputs on multiple CDC338 devices.

Unlike many products containing PLLs, the CDC338 does not require external RC networks. The loop filter for each PLL is included on chip, minimizing component count, board space, and cost. Additionally, each output has its own PLL, which allows mismatches between loads from one output to another.

Because it is based on PLL circuitry, the CDC338 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or feedback signals. Such changes occur upon phase reset of the HF output and upon enable of all outputs. Therefore, stabilization is also required following high-to-low transitions on either or .

The CDC338 is characterized for operation from -40°C to 85°C.