54ACT11109, 74ACT11109
DUAL J-K\ POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET

SCAS451 - FEBRUARY 1987 - REVISED APRIL 1993

features

• Inputs Are TTL-Voltage Compatible
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
• EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

EPIC is a trademark of Texas Instruments Incorporated.

description

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (1 or 2) or clear (1 or 2) input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

The 54ACT11109 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT11109 is characterized for operation from -40°C to 85°C.