SCAS547B - NOVEMBER 1995 - REVISED JUNE 1996
The CDC9161 is an integrated clock synthesizer and driver specifically designed for use with microprocessors manufactured by Intel. The CDC9161 generates the necessary clock signals for a high-performance PC motherboard and provides both 2.5-V and 3.3-V signaling to support both processor/chipset clocks and PCI clocks.
The four host clock (HCLKn) outputs are programmable to 60 MHz or 66 MHz via the SEL control inputs. The eight PCI clock (PCLKn) outputs are one-half the HCLK frequency, and are offset 1 ns to 4 ns from the rising edge of the host clock. In addition, the CDC9161 generates a 48-MHz bus clock (SBCLK), 24-MHz floppy controller clock (FCCLK), 12-MHz keyboard controller clock (KBCLK), three copies of the 14.318-MHz reference clock (REFn), and a 2.5-V IOAPIC clock at 14.318 MHz. All output frequencies are generated from a 14.31818-MHz crystal input.
A test clock can be driven over the XIN input in the test mode. The oscillator and PLLs are bypassed when operating in the test mode.
PLLs are used to generate the host clock and serial bus clock frequencies. On-chip loop filters and internal feedback eliminate the need for external components. The PCI clock frequency is derived from the base host clock frequency; FCCLK and KBCLK are derived from the serial bus clock frequency.
The host and PCI clock outputs provide low-skew/low-jitter clock signals for reliable clock operation. All outputs are 3 state and are disabled via the SEL inputs.
Low-power operation also is provided by the HCLK_EN, PCLK_EN, and PWR_DN\ inputs. HCLK_EN, when low, places all host clocks in the logic low state; all other outputs operate normally. PCLK_EN, when low, places all PCI clocks in the logic low state; all other outputs operate normally. PWR_DN\, when low, suspends all clock outputs and the internal oscillator and PLLs are disabled to a low-power mode.
Because the CDC9161 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the XIN input, as well as following any changes to the SEL inputs or after the return to normal operation following a low-to-high transition of PWR_DN\.