CDC222
1-LINE TO 15-LINE DIFFERENTIAL CLOCK DRIVER

SCAS548A - NOVEMBER 1995 - REVISED JUNE 1996

features

• Low Output Skew for Clock-Distribution and Clock-Generation Applications
• Differential Low-Voltage Pseudo-ECL (LVPECL)-Compatible Inputs and Outputs
• Distributes Differential Clock Inputs to 15 Differential Clock Outputs
• Output Reference Voltage, V_REF, Allows Distribution From a Single-Ended Clock Input
• Outputs Configurable to Provide 1X or 1/2X Input Reference Frequency
• Single-Ended LVPECL-Compatible Output Enable
• Packaged in 52-Pin Thin Quad Flat Package

   

description

The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN\) to fifteen pairs of differential clock (Y, Y\) outputs with minimum skew for clock distribution. It is specifically designed for driving 50- transmission lines.

When the master reset (MR) input is in the low state, the 15 differential ouputs switch at the same or one-half the frequency of the differential clock inputs. When MR is in the high state, the 15 differential outputs are forced to static states (Y outputs in the low state, Y\ outputs in the high state), and the divide-by-two outputs are reset. MR is latched on the negative-edge of the CLKIN input so that the Q outputs are always disabled in the low state.

The four output banks are configured as a bank of two, a bank of three, a bank of four, and a bank of six. Each bank may be configured to provide either same-frequency of half-frequency outputs via the SEL inputs.

The voltage-reference (V_BB) output can be strapped to for a single-ended CLKIN input.

The CDC222 is characterized for operation from 0°C to 70°C.