CDC9171
DVD SYSTEM CLOCK SYNTHESIZER

SCAS558B - DECEMBER 1995 - REVISED OCTOBER 1996

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Two Integrated PLLs Provide All Digital Video Disk (DVD) System Frequencies
• Two 27-MHz Reference Clock Outputs
• One 18.432-MHz Reference Clock Output
• One 33.875-MHz Reference Clock Output
• Output Clock Frequencies Derived From an 18.432-MHz Crystal Input
• 3.3-V CMOS Outputs
• Separate Analog Core and Output Supply Voltage
• Internal Loop Filters for Phase-Lock Loops Eliminate the Need for External Components

   

description

The CDC9171 is a high-performance clock synthesizer that generates the required clock signals needed for a DVD system.

The CDC9171 generates all output frequencies from an 18.432-MHz crystal. The 18.432-MHz (FCLK1) reference clock output is buffered from the integrated oscillators. Two integrated phase-lock loops (PLL) synthesize the 27-MHz (FCLK2, FCLK3) and the 33.868-MHz (FCLK4) reference clock outputs from the 18.4320-MHz crystal. The oscillator and PLLs can be bypassed in the TEST mode. When TEST is high, input 1X1 is buffered to all outputs.

All clock outputs provide low-jitter clock signals for reliable clock operation. is used to disable the PLLs and output buffers. When low, disables the integrated PLLs and forces all outputs to a logic-low state.

Because the CDC9171 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the 1X1 input and upon activation, following the transition of to a logic-high state.