CDC2587
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS

SCAS560B - DECEMBER 1995 - REVISED JULY 1996

features

• Low-Output Skew and Jitter for Clock Distribution and Synchronization
• Operates at 3.3-V V_CC
• Distributes One Clock Input to 16 Outputs
• Four Select Inputs Configure Output Frequency
• Internal Loop Filter Eliminates the Need for External RC Network
• Dedicated External Feedback Output and Input for Phase Synchronization With the Clock Input
• Applications for Synchronous DRAM, High-Speed Microprocessors, and SSTL_3 Applications
• LVTTL- or SSTL_3-Compatible Inputs and Outputs
• Distributed V_CC and GND Pin Configuration Minimize High-Speed Switching Noise
• Meets SSTL_3 Class 1 and 2 Specifications
• Packaged in 56-Pin Plastic Small-Outline Package

description

The CDC2587 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. The CDC2587 operates at 3.3-V V_CC and provides LVTTL- or SSTL_3-compatible inputs and outputs. The CDC2587 operates at frequencies from 16.67 MHz to 150 MHz, and is ideally suited for high-speed microprocessor and synchronous DRAM applications. The CDC2587 provides integrated 25- series damping resistors to improve signal integrity.

A dedicated feedback output (FBOUT) is used to synchronize the output clocks in frequency and phase to the CLKIN reference. Four banks of four outputs (1Yn, 2Yn, 3Yn, 4Yn) are configured to operate at specified ratios of the input frequency by four select (SELn) inputs . Selectable ratios of the input frequency are 1X, 2X, 3X, 1/2X, and 1/3X.

The output-enable () input provides control for the Y output banks. When is high, the outputs are in a high-impedance state. When is low, the outputs switch in accordance with the select inputs. RESET provides a master reset for the CDC2587 counter circuitry. This allows the outputs to be reset to a known state. TEST provides a bypass of the integrated PLL and divider circuitry. When TEST is high, CLKIN bypasses the PLL and is buffered directly to the outputs.

The loop filter components of the PLL are integrated on the CDC2587. This reduces the need for external loop components and provides an easily implemented PLL circuit. FBOUT should be connected to the feedback input (FBIN) for normal operation of the PLL.

The voltage-controlled oscillator (VCO) of the integrated PLL has an operating range of 100 MHz to 300 MHz. The VCO is designed to operate at two to twelve times the CLKIN frequency. This allows the CDC2587 to achieve output frequencies from 16.67 MHz to 150 MHz, with a duty cycle of 50% ± 5% ensured.

Independent analog V_CC (AV_CC) and ground (AGND) connections are provided for VCO stability.

CLKIN and FBIN can be configured to switch at SSTL_3 input levels by connecting V_REF to a nominal reference voltage of 1.5 V. If V_REF is strapped to GND, CLKIN and FBIN switch at normal TTL input thresholds.

Because the CDC2587 is based on PLL technology, it requires a stabilization time to achieve phase lock of the feedback signal to the CLKIN reference. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN. In addition, a stabilization time may be required, following changes to the SELn inputs, TEST inputs, or a change in frequency of CLKIN.