CDC9163
PC CLOCK SYNTHESIZER/DRIVER
WITH SDRAM CLOCK SUPPORT

SCAS574 - JULY 1996

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Clock Generation for Pentium^®/430VX Motherboards
• Twelve Host Clock Outputs With Programmable Frequency
• Six PCI Clock Outputs
• One Serial Bus 48-MHz Clock
• One Floppy Controller 24-MHz Clock
• Two Reference 14.318-MHz Clock Outputs
• All Output Clock Frequencies Derived From a Single 14.31818-MHz Crystal Input
• Internal Loop Filters for Phase-Lock Loops (PLLs)
• Power-Down Modes
• Packaged in Plastic Shrink Small-Outline Package

Pentium is a trademark of Intel Corporation.

description

The CDC9163 is an integrated clock synthesizer specifically designed for use in Pentium^®/430VX based motherboards. Twelve host clock outputs (HCLKn) are programmable via the SEL(0:2) control inputs. This allows four HCLK clocks for use with the processor and chipset, and eight HCLK clocks for use with synchronous DRAM dual in-line memory modules (SDRAM DIMM). The CDC9163 provides six copies of the PCI clock (PCIn), which can be disabled via the control input. All PCI clocks operate at one-half the host clock frequency, and are offset 1 ns to 4 ns from the rising edge of the host clock. In addition, the CDC9163 generates a 48-MHz serial bus clock (SBCLK), a 24-MHz floppy controller clock, and two copies of the 14.318-MHz reference clock (REFn). All output frequencies are generated from a 14.31818-MHz crystal or oscillator input.

PLLs are used to generate the host clock and serial bus clock frequencies. On-chip loop filters and internal feedback eliminate the need for external components. The PCI clock frequency is derived from the base host clock frequency, while the floppy controller clock is derived from the serial bus clock frequency.

The host and PCI clock outputs provide low-skew/low-jitter clock signals for reliable clock operation. All outputs are 3 state and are disabled via the output-enable (OE) input. When OE is high, all outputs are enabled. When OE is low, the outputs are disabled to a high-impedance state. An internal pullup resistor is provided on OE.

Low-power operation also is provided for with and inputs. , when low, places all host clocks in the logic low state; all other outputs operate normally. , when low, places all PCI clocks in the logic low state; all other outputs operate normally. Internal pulldown resistors are provided on the and inputs.

Because the CDC9163 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power-up and application of a fixed-frequency, fixed-phase signal at the XIN input, as well as following any changes to SEL(0:2).