CDC9441
PC CLOCK SYNTHESIZER/DRIVER
WITH SDRAM CLOCK SUPPORT

SCAS578 - AUGUST 1996

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Clock Generation for Intel 440LX Chipset
• Four CPU Clock Outputs With Programmable Frequency
• Twelve SDRAM Clock Outputs
• Seven PCI Clock Outputs
• One 14.318-MHz Reference Clock Output
• All Output Clock Frequencies Derived From a Single 14.31818-MHz Crystal Input
• Internal Loop Filter for Phase-Lock Loop (PLL)
• Selectable Desktop or Mobile Function

description

The CDC9441 is a system clock synthesizer for use in personal computer systems utilizing the Intel 440LX chipset. An integrated crystal oscillator generates a 14.318-MHz reference frequency, while an integrated PLL generates a selectable CPU clock frequency from a 14.31818-MHz crystal input.

The CDC9441 provides four 2.5-V copies of the CPU clock, 12 3.3-V copies of the CPU frequency for use by SDRAM, seven 3.3-V copies of one-half the CPU frequency for PCI, two 2.5-V copies of the 14.318-MHz clock for APIC use, and one 3.3-V copy of the 14.318-MHz output for use as an ISA reference clock.

CPU output frequencies are selectable to either 60 MHz or 66.67 MHz. The output frequency is determined by the SEL control input. When SEL = L, the nominal CPU clock output frequency is 60 MHz. When SEL = H, the nominal CPU clock output frequency is 66.67 MHz. SEL has an integrated pullup resistor, so the default CPU output frequency is 66.67 MHz.

Two modes of operation are offered, desktop and mobile. The device configuration is selected via the MODE control input. When MODE = H, the device is in the desktop configuration. When MODE = L, the device is in the mobile configuration. In the desktop configuration, pins 31, 29, and 28 are outputs SDRAM5, SDRAM6, and SDRAM7, respectively. However, when in the mobile configuration, pins 31, 29, and 28 are power-down enable (), CPU clock bank-enable (CPUEN), and PCI bank-enable (PCIEN) inputs, respectively.

The CDC9441 also provides a serial interface bus for additional control of the device. Each output can be individually enabled or disabled by setting the appropriate control bits within the serial bus register space. A PLL bypass (TEST) mode and output 3-state also can be enabled by setting the appropriate bits in the serial bus register space.

The CDC9441 is characterized for operation from 0°C to 70°C.