SN74BCT298468-BIT BUS-INTERFACE D-TYPE LATCHWITH 3-STATE OUTPUTS

SCBS023C - MARCH 1989 - REVISED APRIL 1994

features

• BiCMOS Process With CMOS Inputs and TTL Outputs Substantially Reduces Standby Current
• Input Has 50- Pullup Resister
• Bus-Structured Pinout
• Functionally Equivalent to SN74ALS29846 and AMD Am29846
• Provides Extra Data Width Necessary For Wider Address/Data Paths or Buses With Parity
• Power-Up High-Impedance State
• Buffered Control Inputs to Reduce DC Loading Effects
• Packaged in Standard Plastic 300-mil DIP (NT)

description

The SN74BCT29846 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the SN74BCT29846 are transparent D-type latches. The SN74BCT29846 has inverting data (D\) inputs. Since clear () and preset () are independent of the clock, taking the input low will cause the eight Q outputs to go low. Taking the input low will cause the eight Q outputs to go high. When both and are taken low, the outputs will follow the preset condition.

The buffered output-enable (, , and ) inputs can be used to place the eight outputs in either a normal logic state (high or low levels) or a high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered-down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive the bus lines in a bus-organized system without need for interface or pull-up components. The output enables do not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN74BCT29846 is characterized for operation from 0°C to 70°C.