SN64BCT373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS

SCBS065A - JUNE 1990 - REVISED JANUARY 1994

features

• State-of-the-Art BiCMOS Design Significantly Reduces I_CCZ
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• High-Impedance State During Power Up and Power Down
• 3-State True Outputs Drive Bus Lines or Buffer-Memory Address Registers
• Full Parallel Access for Loading
• Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (N)

description

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the SN64BCT373 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the enable is taken low, the Q outputs are latched at the levels that were set up at the D inputs.

A buffered output-enable () input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The high-impedance impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

The output-enable () does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.

The outputs are in a high-impedance state during power up and power down while the supply voltage is less than approximately 3 V.

The SN64BCT373 is characterized for operation from -40°C to 85°C and 0°C to 70°C.