) input low,
the device enters data on the low-to-high transition of the clock.
Taking high disables
the clock buffer, thus latching the outputs. Taking the clear (
) input low causes the eight Q
outputs to go low independently of the clock.SCBS075A - SEPTEMBER 1991 - REVISED NOVEMBER 1993
These 8-bit bus-interface flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
The eight flip-flops are edge-triggered D-type flip-flops. With
the clock-enable () input low,
the device enters data on the low-to-high transition of the clock.
Taking high disables
the clock buffer, thus latching the outputs. Taking the clear () input low causes the eight Q
outputs to go low independently of the clock.
Buffered output-enable (
,
, or
) inputs can be used to place the
eight outputs in either a normal logic state (high or low) or a
high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The
high-impedance state and increased drive provide the capability to
drive bus lines without need for interface or pullup components.
The output-enable inputs do not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54BCT29825 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT29825 is characterized for operation from 0°C to 70°C.