SN74BCT956OCTAL BUS TRANSCEIVER AND LATCHWITH 3-STATE OUTPUTS

SCBS088A - NOVEMBER 1991 - REVISED NOVEMBER 1993

features

• State-of-the-Art BiCMOS Design Significantly Reduces I_CCZ
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch Version of the ´BCT646
• Independent Latches and Enables for A and B Buses
• Multiplexed Real-Time and Stored Data
• Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)

description

The SN74BCT956 consists of bus transceiver circuits, D-type latches, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal latches. Data on the A or B bus is stored in the latches when the appropriate latch-enable (LEAB or LEBA) input is low. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74BCT956.

Output-enable () and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode ( low), data present at the high-impedance port may be stored in either latch or in both.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. When the appropriate latch-enable input is high, the latch is transparent, and real-time data is output regardless of the level at the select control.

The direction control (DIR) determines which bus receives data when is low. In the isolation mode ( high), A data may be stored in one register and/or B data may be stored in the other register.

When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time.

The SN74BCT956 is characterized for operation from 0°C to 70°C.