SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995

features

• Free-Running CLKA and CLKB Can Be Asynchronous or Coincident
• 64 × 36 Clocked FIFO Buffering Data From Port A to Port B
• Mailbox-Bypass Register In Each Direction
• Programmable Almost-Full and Almost-Empty Flags
• Microprocessor Interface Control Logic
• Full Flag () and Almost-Full Flag () Synchronized by CLKA
• Empty Flag () and Almost-Empty Flag () Synchronized by CLKB
• Passive Parity Checking on Each Port
• Parity Generation Can Be Selected for Each Port
• Low-Power Advanced BiCMOS Technology
• Supports Clock Frequencies up to 67 MHz
• Fast Access Times of 10 ns
• Available in Space-Saving 120-Pin Thin Quad Flat (PCB) and 132-Pin Plastic Quad Flat (PQ) Packages

description

The SN74ABT3611 is a high-speed, low-power BiCMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10 ns. A 64 × 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words are stored in memory. Communication between each port can take place through two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider datapaths.

The SN74ABT3611 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The full flag () and almost-full flag () of the FIFO are two-stage synchronized to the port clock that writes data to its array (CLKA). The empty flag () and almost-empty () flag of the FIFO are two-stage synchronized to the port clock that reads data from array (CLKB).

The SN74ABT3611 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the application reports FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control and Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications in the 1996 High-Performance FIFO Memories Designer's Handbook, literature number SCAA012A.