SN74LVT18504
3.3-V ABT SCAN TEST DEVICE
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS163F - AUGUST 1993 - REVISED JULY 1996

features

• Member of the Texas Instruments SCOPE ^TM Family of Testability Products
• Member of the Texas Instruments Widebus^TM Family
• State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
• Supports Unregulated Battery Operation Down to 2.7 V
• UBT ^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• SCOPE ^TM Instruction Set
  • IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
  • Parallel-Signature Analysis at Inputs
  • Pseudo-Random Pattern Generation From Outputs
  • Sample Inputs/Toggle Outputs
  • Binary Count From Outputs
  • Device Identification
  • Even-Parity Opcodes
• Packaged in 64-Pin Plastic Thin Quad Flat Packages Using 0.5-mm Center-to-Center Spacings

  SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.

   

description

The SN74LVT18504 scan test device with 20-bit universal bus transceivers is a member of the Texas Instruments SCOPE^TM testability integrated circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, this device is designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

In the normal mode, this device is a 20-bit universal bus transceiver that combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE^TM universal bus transceivers.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA), clock-enable ( and ), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and is low, A-bus data is stored on a low-to-high transition of CLKAB. When is low, the B outputs are active. When is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow but uses the , LEBA, , and CLKBA inputs.

In the test mode, the normal operation of the SCOPE^TM universal bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74LVT18504 is characterized for operation from -40°C to 85°C.