SN74FB2043
7-BIT TTL/BTL TRANSCEIVER

SCBS224A - NOVEMBER 1991 - REVISED JANUARY 1994

features

• Compatible With IEEE 1194.1-1991 (BTL) and IEEE 896.2-1991 (Futurebus+) Standards
• TTL A Port, Backplane Transceiver Logic
  B Port
• Open-Collector B-Port Outputs Sink 100 mA
• Minimum B-Port Edge Rate = 2 ns
• Isolated Logic-Ground and Bus-Ground Pins Reduce Noise
• BIAS V_CC Pin Minimizes Signal Distortion During Live Insertion/Withdrawal
• Packaged in Plastic Quad-Flat Packages (RC) With 0.65-mm Pin Pitches
• B-Port Biasing Network Preconditions the Connector and PC Trace to the Backplane Transceiver Logic High-Level Voltage

   

description

The SN74FB2043 is a 7-bit transceiver designed to translate signals between TTL and backplane transceiver logic (BTL) environments. It is specifically designed to be compatible with IEEE 1194.1-1991 (BTL) and IEEE 896.2-1991 (Futurebus+) standards.

The B port operates at BTL-signal levels. The open-collector B ports are specified to sink 100 mA and have minimum output edge rates of 2 ns. Two output enables, OEB and , are provided for the B outputs. When OEB is high and is low, the B port is active and reflects the data present at the A-input pins. When OEB is low, is high, or V_CC is typically less than 2.5 V, the B port is turned off. The enable/disable logic partitions the device as two 3-bit sections and one 1-bit section.

The A port operates at TTL-signal levels and has split input and output pins. The A outputs reflect the data at the B port when the A-port output enable, OEA, is high. When OEA is low or when V_CC is typically less than 2.5 V, the A outputs are in the high-impedance state.

Pins are allocated for the four-wire IEEE 1149.1 (JTAG) test bus, which will be implemented in a future version of the SN74FB2043. Currently TMS and TCK are not connected and TDI is shorted to TDO.

BIAS V_CC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when V_CC is not connected.

The SN74FB2043 is characterized for operation from 0°C to 70°C.