SN54ABT162600, SN74ABT162600
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS246 - JUNE 1992 - REVISED OCTOBER 1992

features

• B-Port Outputs Have Equivalent 25- Series Resistors, So No External Resistors Are Required
• Members of the Texas Instruments Widebus^TM Family
• State-of-the-Art EPIC-IIB ^TM BiCMOS Design Significantly Reduces Power Dissipation
• UBT ^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical V_OLP (Output Ground Bounce)< 0.8 V at V_CC = 5 V, T_A = 25°C
• Flow-Through Architecture Optimizes PCB Layout
• Packaged in Plastic 300-mil Shrink Small-Outline Packages and 380-mil Fine-Pitch Ceramic Flat Packages Using 25-mil Center-to-Center Spacings

Widebus, EPIC-IIB, and UBT are trademarks of Texas Instruments Incorporated.

description

These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA), and clock ( and ) inputs. The clock can be controlled by the clock-enable ( and) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the high-to-low transition of . Output-enable is active-low. When is low, the outputs are active. When is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses , LEBA, , and.

The B-port outputs, which are designed to source or sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74ABT162600 is available in TI's shrink small-outline package (DL), which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The SN54ABT162600 is characterized over the full military temperature range of -55°C to 125°C. The SN74ABT162600 is characterized for operation from -40°C to 85°C.