SN74BCT29834
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER

SCBS256 - SEPTEMBER 1987 - REVISED NOVEMBER 1993

features

• BiCMOS Process With TTL Inputs and Outputs
• BiCMOS Design Reduces Standby Current
• Flow-Through Pinout (All Inputs on Opposite Side From Outputs)
• Functionally Equivalent to SN74ALS29834 and AMD Am29834
• High-Speed Bus Transceiver With Parity Generator/Checker
• Parity-Error Flag With Open-Collector Output
• Available Register For Storage of the Parity-Error Flag
• Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)

description

The SN74BCT29834 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error () output will indicate whether or not an error in the B data has occurred. The output-enable (, ) inputs can be used to disable the device so that the buses are effectively isolated.

A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error flag (). is clocked into the register on the rising edge of the CLK input. The error flag register is cleared with a low pulse on the clear () input. When both and are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29834 provides inverting logic.

The SN74BCT29834 is characterized for operation from 0°C to 70°C.