SN74LVT16615
17-BIT GTL/LVT UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS

SCBS264 - MARCH 1993

features

• Translates Between GTL Signal Levels and LVCMOS, LVTTL, or 5-V TTL Signal Levels
• Member of the Texas Instruments Widebus^TM Family
• Supports Mixed-Mode Signal Operation on A Port (5-V Input and Output Voltages With 3.3-V V_CC)
• State-of-the-Art BiCMOS Design for Low-Static Power Dissipation
• UBT ^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops With Qualified Storage Enable
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors on A Port
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Flow-Through Architecture Optimizes PCB Layout
• Packaged in Plastic 300-mil Shrink Small-Outline and Thin Shrink Small-Outline Packages

Widebus and UBT are trademarks of Texas Instruments Incorporated.

description

This 17-bit registered bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. It provides for a copy of CLKAB at GTL logic levels (CLKOUT). It also provides a conversion of the GTL clock to a TTL environment (CLKIN).

The B port operates at GTL levels while the A port and control pins are compatible with LVCMOS, LVTTL, or 5-V TTL logic levels.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock or latch-enable can be controlled by the chip-enable ( and ) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if is low and CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if is also low. Output-enable is active-low. When is low, the outputs are active. When is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses , LEBA, CLKBA, and.

To ensure the high-impedance state during power-up or power-down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVT16615 is available in TI's shrink small-outline package (DL), which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The SN74LVT16615 is characterized for operation from 0°C to 70°C.