SN74BCT29824
9-BIT BUS-INTERFACE FLIP-FLOPWITH 3-STATE OUTPUTS

SCBS266 - JULY 1991 - REVISED NOVEMBER 1993

features

• State-of-the-Art BiCMOS Design Significantly Reduces I_CCZ
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• 3-State Buffer-Type Outputs Drive Bus Lines Directly
• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

description

This 9-bit bus-interface flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The nine flip-flops are edge-triggered D-type flip-flops. With the clock-enable () input low, the flip-flops store data on the low-to-high transitions of the clock. Taking high disables the clock buffer, thus latching the outputs. The SN74BCT29824 has inverting data (D\) inputs. Taking the clear () input low causes the nine Q outputs to go low independent of the clock.

A buffered output-enable () input can be used to place the nine outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

The output enable () does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN74BCT29824 is characterized for operation from 0°C to 70°C.