SN74ABT38652
36-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS

features

• Member of the Texas Instruments Widebus+^TM Family
• State-of-the-Art EPIC-IIB ^TM BiCMOS Design Significantly Reduces Power Dissipation
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Compatible With the IEEE Standard 1149.1 (JTAG) Serial Test Bus
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 5 V, T_A = 25°C
• Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
• High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
• Bus-Hold Inputs Eliminate the Need for External Pullup Resistors
• Packaged in 120-Pin Cavity-Shrink Quad Flat Pack With 14 × 14-mm Package Body Using 0.4-mm Lead Pitch

  Widebus+ and EPIC-IIB are trademarks of Texas Instruments Incorporated.

  
  

description

The SN74ABT38652 is a 36-bit (quad 9-bit) bus transceiver that consists of D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. This device can be used as four 9-bit transceivers, two 18-bit transceivers, or one 36-bit transceiver.

Output-enable (OEAB and ) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and a high input selects stored data.

Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and . In this configuration each output reinforces its input. Therefore, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remain at its last state.

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver (B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver (A to B).

Active bus-hold circuitry is provided to hold unused or floating inputs at a valid logic level.

The SN74ABT38652 is characterized for operation from -40°C to 85°C.