SN74ABT32360
16-BIT UNIVERSAL TRI-PORT
WITH PARITY GENERATORS/CHECKERS

features

• Member of the Texas Instruments Widebus+^TM Family
• State-of-the-Art EPIC-IIB ^TM BiCMOS Design Significantly Reduces Power Dissipation
• UBE ^TM (Universal Bus Exchanger) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode
• Simultaneously Generates and Checks Parity
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 5 V, T_A = 25°C
• Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
• High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
• Bus-Hold Inputs Eliminate the Need for External Pullup Resistors
• Packaged in 100-Pin Plastic Thin Quad Flat Pack (TQFP) With 14 × 14-mm Package Body Using 0.5-mm Lead Pitch

   

  Widebus+ and EPIC-IIB are trademarks of Texas Instruments Incorporated.

description

The 'ABT32360 consists of three 16-bit registered input/output (I/O) ports. These registers combine D-type latches and flip-flops to allow data flow in transparent, latch, and clock modes. Data from one input port can be exchanged to one or more of the other ports. Because of the universal storage element, multiple combinations of real-time and stored data can be exchanged among the three ports.

Data flow in each direction is controlled by the output-enable (, , and ), select-control (SELA, SELB, and SELC), latch-enable (LEA, LEB, and LEC), and clock enable (, , and ) inputs. The A-data register operates in the transparent mode when LEA is high. When LEA is low, data is latched if CLK is held at a high or low logic level. If LEA and clock-enable A () are low, data is stored on the low-to-high transition of CLKA. B and C ports operate identically. Output data selection is accomplished by the select-control pins. All three ports have active-low output enables, so when the output-enable input is low, the outputs are active (assuming LEO is high); when the output-enable input is high, the outputs are in the high-impedance state. Additionally, a synchronous output enable feature is provided which is activated when LEO is held low. If is asserted, is activated on the rising edge of CLK and the outputs are enabled or disabled depending upon the level of .

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54ABT32360 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT32360 is characterized for operation from -40°C to 85°C.