SN54GTL16616, SN74GTL16616
17-BIT GTL/LVT UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS

SCBS481D - JUNE 1994 - REVISED NOVEMBER 1996

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Translate Between GTL Signal Levels and LVTTL or 5-V TTL Signal Levels
• Members of the Texas Instruments Widebus^TM Family
• Support Mixed-Mode Signal Operation on A Port
• Universal Bus Transceiver (UBT^TM) Combines D-Type Latches and D-Type Flip-Flops With Qualified Storage Enable
• Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors on A Port
• Flow-Through Architecture Facilitates Printed-Circuit-Board Layout
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Ceramic Flat (WD) Packages

Widebus and UBT are trademarks of Texas Instruments Incorporated.

description

These 17-bit registered bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. The 'GTL16616 provide for a copy of CLKAB at GTL logic levels (CLKOUT) and also provide a conversion of the GTL clock to a TTL environment (CLKIN).

The B port operates at GTL levels while the A port and control inputs are compatible with LVCMOS, LVTTL, or 5-V TTL logic levels.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock or latch-enable can be controlled by the clock-enable ( and ) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if is low and CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if is also low. is active low. When is low, the outputs are active. When is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses , LEBA, CLKBA, and.

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74GTL16616 is available in TI's shrink small-outline package (DL), which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The SN54GTL16616 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74GTL16616 is characterized for operation from -40°C to 85°C.