SN54ABT8373, SN74ABT8373
SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES

SCBS487 - JULY 1994

features

• Members of the Texas Instruments SCOPE ^TM Family of Testability Products
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port
  and Boundary-Scan Architecture
• Functionally Equivalent to SN54/74F373 and SN54/74ABT373 in the Normal- Function Mode
• SCOPE ^TM Instruction Set:
  • IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP and HIGHZ
  • Parallel-Signature Analysis at Inputs With Masking Option
  • Pseudo-Random Pattern Generation From Outputs
  • Sample Inputs/Toggle Outputs
  • Binary Count From Outputs
  • Even-Parity Opcodes
• State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
• Package Options Include Plastic Small-Outline Packages (DW), Ceramic Chip Carriers (FK), and Standard Ceramic DIPs (JT)

  SCOPE and EPIC-IIB are trademarks of Texas Instruments Incorporated.

description

The SN54ABT8373 and SN74ABT8373 scan test devices with octal D-type latches are members of the Texas Instruments SCOPE^TM testability integrated circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the SN54/74F373 and SN54/74ABT373 octal D-type latches. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPE^TM octal D-type latches.

In the test mode, the normal operation of the SCOPE^TM D-type latches is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.

Four dedicated test pins are used to control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT8373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT8373 is characterized for operation from -40°C to 85°C.