SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS

SCES010B - JULY 1995 - REVISED NOVEMBER 1996

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Member of the Texas Instruments Widebus+^TM Family
• EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
• UBT^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• Simultaneously Generates and Checks Parity
• Option to Select Generate Parity and Check or Feed-Through Data/Parity in A-to-B or B-to-A Directions
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Packaged in Thin Shrink Small-Outline Package

  Widebus+, EPIC, and UBT are trademarks of Texas Instruments Incorporated.

description

This 18-bit (dual-octal) noninverting registered transceiver is designed for 2.3-V to 3.6-V V_CC operation.

The SN74ALVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction.

The SN74ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable ( or) inputs. It also provides parity-enable () and parity-select (ODD/) inputs and separate error-signal (or ) outputs for checking parity. The direction of data flow is controlled by and. When is low, the parity functions are enabled. When is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver.

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16901 is available in TI's thin shrink small-outline (DGG) package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed circuit board area.

The SN74ALVCH16901 is characterized for operation from -40°C to 85°C.