SN74ALVCH16500
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS

SCES023C - JULY 1995 - REVISED NOVEMBER 1996

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Member of the Texas Instruments Widebus^TM Family
• EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
• UBT^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds
  200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.

EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.

description

This 18-bit universal bus transceiver is designed for 2.3-V to 3.6-V V_CC operation.

Data flow in each direction is controlled by output-enable (OEAB and ), latch-enable (LEAB and LEBA), and clock ( and ) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if is held at a high or low logic level. If LEAB

is low, the A-bus data is stored in the latch/flip-flop on the high-to-low transition of. Output-enable OEAB is active high. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses , LEBA, and. The output enables are complementary (OEAB is active high, and is active low).

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16500 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed circuit board area.

The SN74ALVCH16500 is characterized for operation from -40°C to 85°C.