and 
) and clock (CLKAB and CLKBA)
inputs. The clock-enable (
and
) inputs are
designed to control each 9-bit transceiver independently, which makes
the device more versatile.
SCES049C - AUGUST 1995 - REVISED OCTOBER 1996
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
These 18-bit registered bus transceivers contain two sets of D-type flip-flops for temporary storage of data flowing in either direction.
The B port operates at GTL (VTT = 1.2 V and VREF = 0.8 V) and GTL+ (VTT = 1.5 V and VREF = 1 V) levels, while the A port and control inputs are compatible with LVTTL logic levels.
Data flow in each direction is controlled by output-enable ( and ) and clock (CLKAB and CLKBA)
inputs. The clock-enable ( and
) inputs are
designed to control each 9-bit transceiver independently, which makes
the device more versatile.
For A-to-B data flow, the devices operate on the low-to-high
transition of CLKAB if is
low. When is low, the
outputs are active. When is
high, the outputs are in the high-impedance state. Data flow for B to
A is similar to that for A to B, but uses , CLKBA, and .
Active bus-hold circuitry is provided to hold unused or floating TTL inputs at a valid logic state.
To ensure the high-impedance state during power up or power down,
should be tied
to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the
driver.
The SN54GTL16622 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74GTL16622 is characterized for operation from -40°C to 85°C.
A-to-B data flow is shown: B-to-A data flow is similar but
uses , CLKBA, and
.
Output level before the indicated steady-state input conditions are established