inputs are low. A two-stage
pipeline is provided in each of the A-to-1B and A-to-2B paths to
serve as a shallow write buffer.
SCES057B - OCTOBER 1995 - REVISED JANUARY 1997
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
This 12-bit to 24-bit bus exchanger is designed for 2.3-V to 3.3-V VCC operation.
The SN74ALVCH16272 is intended for applications where two separate datapaths must be multiplexed onto, or demultiplexed from, a single datapath. This device is particularly suitable as an interface between conventional DRAMs and high-speed microprocessors.
Data from the A inputs is stored in the internal registers on the
low-to-high transition of the clock (CLK) input, when the inputs are low. A two-stage
pipeline is provided in each of the A-to-1B and A-to-2B paths to
serve as a shallow write buffer.
Transparent latches are provided in the B-to-A path to allow
asynchronous operation to maximize memory access throughput. These
latches transfer data when the latch-enable (
) inputs are low. The select (
) line selects 1B or 2B data for
the A outputs. Data flow is controlled by the active-low output
enables (
, 
).
To ensure the high-impedance state during power up or power down,
should be tied
to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the
driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16272 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed circuit board area.
The SN74ALVCH16272 is characterized for operation from -40°C to 85°C.