SN54ALVTH16646, SN74ALVTH16646
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCES072A - JUNE 1996 - REVISED JULY 1996

features

• Members of the Texas Instruments Widebus^TM Family
• High-Impedance State During Power Up and Power Down
• 5-V I/O Compatible
• High-Drive Outputs (-32 mA/64 mA)
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Auto 3-State Eliminates Bus Current Loading When Voltage at the Output Exceeds V_CC
• Bus-Hold Data Inputs Eliminate the Need for External Pullup/Pulldown Resistors
• Power Off Disables Inputs/Outputs, Permitting Live Insertion
• Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package

Widebus is a trademark of Texas Instruments Incorporated.

description

The 'ALVTH16646 are 16-bit bus transceivers designed for 2.5-V or 3.3-V V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ´ALVTH16646.

Output-enable and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when is low. In the isolation mode ( high), A data can be stored in one register and/or B data can be stored in the other register.

When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When V_CC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74ALVTH16646 is available in TI's thin very small-outline package (DGV), which provides the same I/O pin count and functionality of standard Widebus packages in less than half the printed circuit board area.

The SN54ALVTH16646 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16646 is characterized for operation from -40°C to 85°C.

^[dagger] The data output functions can be enabled or disabled by various signals at and DIR. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs.

Figure 1. Bus-Management Functions