SN54ALVTH16841, SN74ALVTH16841
2.5-V/3.3-V 20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCES077A - JULY 1996 - REVISED JULY 1996

features

• Members of the Texas Instruments Widebus^TM Family
• High-Impedance State During Power Up and Power Down
• 5-V I/O Compatible
• High-Drive Capability (-32 mA/64 mA)
• Typical V_OLP (Output Ground Bounce)
  < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Auto 3-State Eliminates Bus Current Loading When Voltage at the Output Exceeds V_CC
• Bus-Hold Data Inputs Eliminate the Need for External Pullup/Pulldown Resistors
• Power Off Disables Inputs/Outputs, Permitting Live Insertion
• Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package

  Widebus is a trademark of Texas Instruments Incorporated.

description

The 'ALVTH16841 are 20-bit bus-interface D-type latches with 3-state outputs designed for 2.5-V or 3.3-V V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The 'ALVTH16841 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, unidirectional bus drivers, and working registers.

The 'ALVTH16841 can be used as two 10-bit latches or one 20-bit latch. The 20 latches are transparent D-type latches. The device has noninverting data (D) inputs and provides truedata at its outputs. While the latch-enable (1 or 2) input is high, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

The output-enable input does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Active bus-hold circuitry is provided to hold unused or floating inputs at a valid logic level.

When V_CC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74ALVTH16841 is available in TI's thin very small-outline package (DGV), which provides the same I/O pin count and functionality of standard Widebus packages in less than half the printed circuit board area.

The SN54ALVTH16841 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16841 is characterized for operation from -40°C to 85°C.