and 
) and clock enable (
) inputs. For the A-to-B data flow, the data flows
through a single register. The B-to-A data can flow through a
four-stage pipeline register path, or through a single register path,
depending on the state of 
.
SCES080 - JULY 1996
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EPIC and Widebus are trademarks of Texas Instruments Incorporated.
This 18-bit universal bus transceiver is designed for 2.3-V to 3.6-V VCC operation.
Data flow in each direction is controlled by output-enable (and ) and clock enable () inputs. For the A-to-B data flow, the data flows
through a single register. The B-to-A data can flow through a
four-stage pipeline register path, or through a single register path,
depending on the state of .
Data is stored in the internal registers on the low-to-high
transition of the CLK input, provided that the appropriate input is low. The B-to-A data
transfer is synchronized with the CLK input.
To ensure the high-impedance state during power up or power down,
should be tied
to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the
driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16524 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.
The SN74ALVCH16524 is characterized for operation from -40°C to 85°C.