SN74ALVCH162831
1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS

SCES084A - AUGUST 1996 - REVISED MAY 1997

Copyright © 1997, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Member of the Texas Instruments Widebus^TM Family
• EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
• Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• Packaged in Plastic 300-mil Thin Shrink Small-Outline Package

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

description

This 1-bit to 4-bit address register/driver is designed for 2.3-V to 3.6-V V_CC operation. The device is ideal for use in applications where a single address bus is driving four separate memory locations. The SN74ALVCH162831 can be used as a buffer or a register, depending on the logic level of the select (SEL\) input.

When SEL\ is logic high, the device is in the buffer mode. The outputs follow the inputs and are controlled by the two output-enable (OE\) controls. Each OE\ controls two groups of nine outputs.

When SEL\ is logic low, the device is in the register mode. The register is an edge-triggered D-type flip-flop. On the positive transition of the clock (CLK) input, data set up at the A inputs is stored in the internal registers. OE\ controls operate the same as in buffer mode.

When OE\ is logic low, the outputs are in a normal logic state (high or low logic level). When OE\ is logic high, the outputs are in high-impedance state.

SEL\ and OE\ do not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162831 is characterized for operation from -40°C to 85°C.