SN74ALVCH162841
20-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS

SCES088A - OCTOBER 1996 - REVISED MARCH 1997

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Member of the Texas Instruments Widebus^TM Family
• EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
• Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required
• Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

   

  EPIC and Widebus are trademarks of Texas Instruments Incorporated.

description

This 20-bit bus-interface D-type latch is designed for 2.3-V to 3.6-V V_CC operation.

The SN74ALVCH162841 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, unidirectional bus drivers, and working registers.

The SN74ALVCH162841 can be used as two 10-bit latches or one 20-bit latch. The 20 latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The outputs, which are designed to sink up to 12 mA, include 26- resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating inputs at a valid logic level.

The SN74ALVCH162841 is characterized for operation from -40°C to 85°C.