SN74HSTL162822
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH

SCES091A - DECEMBER 1996 - REVISED APRIL 1997

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features

• Member of the Texas Instruments Widebus^TM Family
• Inputs Meet JEDEC HSTL Standard JESD8-6
• All Outputs Have Equivalent 25- Series Resistors
• Packaged in Plastic Thin Shrink Small-Outline Package

Widebus is a trademark of Texas Instruments Incorporated.

description

This 14-bit to 28-bit D-type latch is designed for 3.15-V to 3.45-V V_CC operation. HSTL levels are expected on the inputs. LVTTL levels are driven on the Q outputs.

All outputs are designed to sink up to 12 mA and include 25- series resistors to reduce overshoot and undershoot.

The SN74HSTL162822 is particularly suitable for driving an address bus to two banks of memory. Each bank of 14 outputs is controlled with its own latch-enable () input.

Each of the 14 data (D) inputs is tied to the inputs of two D-type latches, which provide true data at the outputs. While LE\ is low, the outputs (Q) of the corresponding 14 latches follow the D inputs. When is taken high, the Q outputs are latched at the levels set up at the D inputs.

The SN74HSTL162822 is characterized for operation from -40°C to 90°C.