SN74HSTL16918
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH

SCES096A - APRIL 1997 - REVISED APRIL 1997

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features

• Member of the Texas Instruments Widebus^TM Family
• Inputs Meet JEDEC HSTL Std JESD 8-6
• Packaged in Plastic Thin Shrink Small-Outline Package

Widebus is a trademark of Texas Instruments Incorporated.

description

This 9-bit to 18-bit D-type latch is designed for 3.15-V to 3.45-V V_CC operation. HSTL levels are expected on the data (D) inputs; LVTTL levels are driven on the Q outputs.

The SN74HSTL16918 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controlled with its own latch-enable () input.

Each of the nine D inputs is tied to the inputs of two D-type latches, which provide true data (Q) at the outputs. While is low, the Q outputs of the corresponding nine latches follow the D inputs. When is taken high, the Q outputs are latched at the levels set up at the D inputs.

The SN74HSTL16918 is characterized for operation from -40°C to 90°C.

Output level before the indicated steady-state input conditions were established