SCES098A - MAY 1997 - REVISED JULY 1997
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
This 1-bit to 4-bit address register/driver is designed for 2.3-V
to 3.6-V VCC operation. This device is ideal for use in
applications where a single address bus is driving four separate
memory locations. The SN74ALVCH16832 can be used as a buffer or a
register, depending on the logic level of the select (
) input.
When
is a logic
high, the device is in the buffer mode. The outputs follow the inputs
and are controlled by the two output-enable (
) controls. Each
controls two groups of seven
outputs.
When
is a logic low,
the device is in the register mode. The register is an edge-triggered
D-type flip-flop. On the positive transition of the clock (CLK)
input, data at the A inputs is stored in the internal registers.
controls operate the same as in the
buffer mode.
When
is a logic low,
the outputs are in a normal logic state (high or low logic level).
When
is a logic
high, the outputs are in the high-impedance state.
Neither
nor
affect the internal operation of
the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down,
should be tied to VCC
through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16832 is characterized for operation from -40°C to 85°C.