SN54LV02, SN74LV02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCLS183B - FEBRUARY 1993 - REVISED APRIL 1996

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• EPIC^TM (Enhanced-Performance Implanted CMOS) 2- Process
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC, T_A = 25°C
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
• Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Ceramic (J) 300-mil DIPs

  EPIC is a trademark of Texas Instruments Incorporated.

description

These quadruple 2-input positive-NOR gates are designed for 2.7-V to 5.5-V V_CC operation.

The 'LV02 perform Boolean function or Y = A\ • B\ in positive logic.

The SN74LV02 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN54LV02 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LV02 is characterized for operation from -40°C to 85°C.