SN54LV373, SN74LV373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCLS196C - FEBRUARY 1993 - REVISED APRIL 1996

features

• EPIC^TM (Enhanced-Performance Implanted CMOS) 2-u Process
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC, T_A = 25°C
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs

  EPIC is a trademark of Texas Instruments Incorporated.

description

These octal transparent D-type latches are designed for 2.7-V to 5.5-V V_CC operation.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN74LV373 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN54LV373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LV373 is characterized for operation from -40°C to 85°C.